In signal processing circuits of the type described above, it is indispensable performance requirements to suppress a carrier leak and prevent the modulation accuracy from being lowered in orthogonal modulators for achieving communication quality and complying with rules and regulations.
The carrier leak corresponds a DC offset of I/O components as converted into an input to the orthogonal modulator. Factors that affect the modulation accuracy of the orthogonal modulator include a variation (a factor responsible for an I/Q mismatch to be described later) in the levels of I/O components as converted into an input to the orthogonal modulator, and a variation (a factor responsible for an I/Q mismatch to be described later) in the orthogonality of a local signal input to the orthogonal modulator, i.e., the amplitudes of and the phase difference between the I/O components.
As the rate of communications has become higher in recent years, however, the above performance requirements, though they have been required to be met at higher levels, tend to be lowered due to circuit limitations posed by a direct conversion architecture and a lower process voltage.
Therefore, it is essential for the signal processing circuit to have a means for compensating for a DC offset and an I/Q mismatch (an I/Q amplitude mismatch and an I/Q phase mismatch) of the orthogonal modulator.
The I/Q amplitude mismatch refers to a discrepancy between the amplitudes of the I/O components of an output signal from the orthogonal modulator. The I/Q amplitude mismatch may be caused by three factors, i.e., (1) a discrepancy between the amplitudes of the I/O components of a local signal input to the orthogonal modulator, (2) a discrepancy between the amplitudes of the I/O components of a transmission baseband signal input to the orthogonal modulator, and (3) a discrepancy between the gains of I and Q component paths in the orthogonal modulator.
The I/Q phase mismatch refers to a deviation from 90 degrees of the phase difference between the I/O components of an output signal from the orthogonal modulator. The I/Q phase mismatch may be caused by three factors, i.e., (1) a deviation from 90 degrees of the phase difference between the I/O components of a local signal input to the orthogonal modulator, (2) a deviation from 90 degrees of the phase difference between the I/O components of a transmission baseband signal input to the orthogonal modulator, and (3) a deviation of the phases of I and Q component paths in the orthogonal modulator.
Heretofore, there have been proposed many signal processing circuits incorporating a means for compensating for a DC offset and an I/Q mismatch of the orthogonal modulator. However, it is ideal for nearly no hardware to be added for compensation. In this respect, much remains to be improved in signal processing circuits of the background art.
FIG. 1 is a diagram showing a structural example of a signal processing circuit of the background art.
As shown in FIG. 1, the signal processing circuit of the background art comprises transmission BB (BaseBand) signal generator 101, test signal generator 103, switch 104, DC offset·I/Q mismatch compensator 102, D/A converters 105I, 105Q, mixers 106I, 106Q, adder 107, envelope detector 108, A/D converter 109, and compensation quantity generator 110.
Transmission BB signal generator 101 generates a transmission baseband signal in a transmitting process.
Test signal generator 103 generates test signals in a compensating process.
Switch 104 selects the test signals generated by test signal generator 103 in the compensating process, and selects the transmission baseband signal generated by transmission BB signal generator 101 in the transmitting process.
In the compensating process, a compensation quantity for compensating for a DC offset and an I/Q mismatch of an orthogonal modulator is set in DC offset·I/Q mismatch compensator 102 by compensation quantity generator 110. In the transmitting process, DC offset·I/Q mismatch compensator 102 corrects the transmission baseband signal generated by transmission BB signal generator 101 based on the compensation quantity set by compensation quantity generator 110.
D/A converter 105I converts the I component of a signal output from DC offset·I/Q mismatch compensator 102 from a digital signal into an analog signal. D/A converter 105Q converts the Q component of the signal output from DC offset·I/Q mismatch compensator 102 from a digital signal into an analog signal.
Mixer 106I upconverts the I component of the signal converted by D/A converter 105I by mixing it with the I component of a local signal. Mixer 106Q upconverts the Q component of the signal converted by D/A converter 105Q by mixing it with the Q component of the local signal.
Adder 107 adds the I component of the signal mixed by mixer 106I and the Q component of the signal mixed by mixer 106Q to each other. The signal that has thus been orthogonally modulated serves as an output signal of the signal processing circuit.
Envelope detector 108 detects the amplitude of the envelope of the output signal from the orthogonal modulator.
A/D converter 109 converts an output signal of envelope detector 108 from an analog signal into a digital signal.
Compensation quantity generator 110 calculates a DC offset quantity and an I/Q mismatch quantity of the orthogonal modulator based on the digital signal from A/D converter 109, generates a compensation quantity for compensating the DC offset and the I/Q mismatch, and sets the generated compensation quantity in DC offset·I/Q mismatch compensator 102.
Operation of the above signal processing circuit of the background art will be described below.
In the compensating process, switch 104 selects the test signals generated by test signal generator 103. The test signals are supplied through DC offset·I/Q mismatch compensator 102 and D/A converters 105I, 105Q to baseband ports of the orthogonal modulator, which orthogonally modulates the test signals. The amplitude of the orthogonally modulated signal is detected by envelope detector 108, and the detected amplitude is converted into a digital signal by A/D converter 109. Based on the digital signal, compensation quantity generator 110 generates a compensation quantity.
FIG. 2 is a diagram showing typical test signals used to perform compensation on the orthogonal modulator. Typically, the test signals include an I component represented by a cosine wave and a Q component represented by a sine wave.
FIG. 3 is a diagram showing the constellation of an output signal from the orthogonal modulator in an ideal state. When the orthogonal modulator is in an ideal state, either one of the I component and the Q component is free of a DC offset, and there is no I/Q amplitude mismatch and no I/Q phase mismatch. In this case, the constellation is represented by a true circle with its center at the origin. Therefore, the envelope of the output signal from the orthogonal modulator is represented by the sine wave of a constant envelope.
FIG. 4 is a diagram showing the constellation of an output signal from the orthogonal modulator which suffers a DC offset. In this case, the constellation is represented by a circle whose center is shifted from the origin. Therefore, the envelope of the output signal from the orthogonal modulator increases and decreases with time.
FIG. 5 is a diagram showing the constellation of an output signal from the orthogonal modulator which suffers an I/Q amplitude mismatch. FIG. 6 is a diagram showing the constellation of an output signal from the orthogonal modulator which suffers an I/Q phase mismatch. In each case, the envelope of the output signal from the orthogonal modulator increases and decreases with time.
Compensation quantity generator 110 checks the period and phase with which the envelope of the output signal from the orthogonal modulator increases and decreases, against the phase and frequency of the test signals thereby to confirm how much DC offset, I/Q amplitude mismatch, and I/Q phase mismatch the orthogonal modulator is suffering, and generates a compensation quantity to be set in DC offset·I/Q mismatch compensator 102.
In the transmitting process, switch 104 selects the transmission baseband signal generated by transmission BB signal generator 101. The transmission baseband signal is input to DC offset·I/Q mismatch compensator 102 and corrected based on the compensation quantity already set in DC offset·I/Q mismatch compensator 102. The corrected signal is supplied through D/A converters 105I, 105Q and input to the baseband ports of the orthogonal modulator, which orthogonally modulates the test signals. The signal that has thus been orthogonally modulated serves as an output signal of the signal processing circuit.
A technology similar to the above technology is disclosed in Patent document 1. Patent document 1 discloses a method of compensating for an I/Q phase mismatch of an orthogonal modulator using only two points in the first through fourth quadrants of an I/Q orthogonal coordinate system. According to this method, test signals are simplified.
Another technology similar to the above technology is disclosed in Patent document 2. Patent document 2 discloses a method of inputting sine-wave test signals to the baseband ports of an orthogonal modulator for compensation.
Still another technology similar to the above technology is disclosed in Patent document 3. Patent document 3 discloses a method of improving the accuracy of an orthogonal modulator based on a signal that is produced when transmission data are converted in frequency by an I/Q orthogonal down converter.
Other technologies similar to the above technology is disclosed in Patent documents 4 through 9.
However, the background art described above has the following problems:
The background art described above with reference to FIGS. 1 through 6 requires a ROM for storing the waveform data of the test signals because the test signals are of a sine wave, needs to operate at an appropriate speed in order to generate smooth test signals, and requires an ND converter for converting the output of the envelope detector from an analog signal into a digital signal.
According to the background art disclosed in Patent document 1, the test signals are simplified because only two points in the I/Q orthogonal coordinate system are used as the test signals. However, Patent document 1 discloses only a method of compensating for an I/Q phase mismatch, but not a method of compensating for an I/Q amplitude mismatch. To compensate for an I/Q phase mismatch according to the method disclosed in Patent document 1, it is necessary that a DC offset as converted into an input to the orthogonal modulator, i.e., a carrier leak as converted into an output from the orthogonal modulator, be suppressed to a sufficiently low level, and an I/Q amplitude mismatch be suppressed to a sufficiently low level.
The method disclosed in Patent document 1 will be described in detail below with reference to FIGS. 7 and 8. It is assumed that two points in the first and second quadrants of an I/Q orthogonal coordinate system are used as test signals for compensating for an I/Q phase mismatch.
FIG. 7 is a diagram showing an example of test signals represented by two points used in the compensating process of an orthogonal modulator. The orthogonal modulator is assumed to be completely free of a DC offset, an I/Q phase mismatch, and an I/Q amplitude mismatch. In FIG. 7, point 5 is a point in the first quadrant, and point 6 is a point in the second quadrant.
According to the method disclosed in Patent document 1, the distance from the origin to point 5 and the distance from the origin to point 6 are determined by detecting the amplitude of the envelope of an output signal from the orthogonal modulator, and a condition for making the distances equal to each other is determined as a condition for the non-existence of an I/Q phase mismatch. If the orthogonal modulator is in an ideal state, therefore, the method disclosed in Patent document 1 obviously functions normally.
However, the orthogonal modulator necessarily suffers an input-converted DC offset because of the problem of its manufacturing accuracy.
FIG. 8 is a diagram showing an example of test signals represented by two points used in the compensating process of an orthogonal modulator if the orthogonal modulator suffers a DC offset. The orthogonal modulator is also assumed to be completely free of an I/Q phase mismatch and an I/Q amplitude mismatch.
The example shown in FIG. 8 is different from the example shown in FIG. 7 in that a positive DC offset is produced in an I component and a negative DC offset in a Q component. Even when there is no input to the orthogonal modulator, therefore, it causes a carrier leak corresponding to point 0′. Because of the DC offsets, points 5, 6 are shifted downwardly and rightwardly to respective points 5′, 6′.
According to the method disclosed in Patent document 1, the distance from the origin to point 5′ and the distance from the origin to point 6′ are determined by detecting the amplitude of the envelope of an output signal from the orthogonal modulator, and a condition for making the distances equal to each other is determined as a condition for the non-existence of an I/Q phase mismatch.
In the example shown in FIG. 8, however, regardless of the fact that there is no I/Q phase mismatch, the distance from the origin to point 5′ is apparently longer than the distance from the origin to point 6′. In other words, if the orthogonal modulator suffers a DC offset, the method disclosed in Patent document 1 does not function normally.
Even if condition for making the distance from the origin to point 5 and the distance from the origin to point 6 equal to each other is determined in the example shown in FIG. 7, it is necessary that an I/Q amplitude mismatch quantity be known in order to determine an I/Q phase mismatch quantity as an angle or its sine-wave function based on the amplitudes of I and Q components of test signals at the time. In other words, in order to know two unknown quantities, i.e., an I/Q amplitude mismatch quantity and an I/Q phase mismatch quantity, only one equation representing that the distance from the origin to point 5 and the distance from the origin to point 6 are equal to each other is not enough, but another equation is necessary. Actually, the equations disclosed in Patent document 1 do not taken into account the effect of an I/Q amplitude mismatch.
It is assumed that when two points (I,Q)=(1.05, 1.00), (−0.95, 1.00) are input as test signals to an orthogonal modulator, the signal intensities of output signals from the orthogonal modulator are equal to each other and the orthogonal modulator suffers an I/Q amplitude mismatch in which the amplitude of the I component is k times greater than the amplitude of the Q component. If an I/Q phase mismatch quantity is indicated by X, then the following equation 1 is satisfied:(1.00 cos X)2+(1.05k+1.00 sin X)2=(1.00 cos X)2+(0.95k+1.00 sin X)2  [Equation 1]
Therefore, it will be understood that unless k is known beforehand, the I/Q phase mismatch quantity X cannot be determined.
To avoid the above problem, the DC offset and the I/Q amplitude mismatch of the orthogonal modulator may be compensated for by another method according to the background art before the method disclosed in Patent document 1 is carrier out.
In reality, however, it is necessary to use a D/A converter for compensating for a DC offset. When a D/A converter is used, a certain DC offset inevitably remains due to the resolution of the D/A converter. In addition, the amount of a carrier leak allowed by the ordinary wireless communication system, i.e., the value of a DC offset as converted into an input to the orthogonal modulator, is allowed to have a relatively large value in the range from −15 to +20 dB with respect to the total transmission power. Nevertheless, using the method disclosed in Patent document 1 requires a DC offset to be removed with much higher accuracy than the amount of the DC offset allowed by the wireless communication system, bringing about packaging complexities.
The background art disclosed in Patent document 2 is problematic in that it requires a complex system including a test signal generator for generating sine-wave test signals and an ND converter.
The background art disclosed in Patent document 3 is problematic in that it requires a complex system and, additionally, the I/Q accuracy of an I/Q orthogonal downconverter used for a compensating process is responsible for an error of the compensating process. Specifically, a highly accurate compensating process requires an I/Q orthogonal downconverter having a high I/Q accuracy. However, a compensating process is performed because an orthogonal modulator having a high modulating accuracy is not practically available, and it is contradictory to require an I/Q orthogonal downconverter having a high I/Q accuracy as a means for such a compensating process.
The background art disclosed in Patent documents 4, 5 is also problematic in that it requires a complex system including a test signal generator and an A/D converter. However, no means for solving the problems is disclosed in Patent documents 4, 5.
According to the background art disclosed in Patent document 6, four points on a phase plane where the signal intensities of output signals from an orthogonal modulator are determined to simultaneously determine quantities for compensating an I/Q phase mismatch and a DC offset. However, the background art disclosed in Patent document 6 also requires an A/D converter. It is also necessary to determine compensating quantities by solving four simultaneous equations with 12 variables shown as the equations (6) in Patent document 6, based on the data obtained within the range of the limited resolution of the A/D converter. Consequently, a piece of hardware needs to be added for solving the four simultaneous equations, and the accuracy of the compensating quantities is low. Nothing is disclosed in Patent document 6 for meeting the need for an I/Q amplitude mismatch quantity to be determined beforehand.
According to the background art disclosed in Patent document 7, a compensation quantity for compensating for an I/Q amplitude mismatch is determined from three items of information, i.e., the signal intensities of input signals to an orthogonal modulator and the signal intensity of an output signal from the orthogonal modulator. However, the background art disclosed in Patent document 7 also requires an A/D converter. No consideration is given to the effect that a DC offset and an I/Q phase mismatch have on the signal intensity of the output signal from the orthogonal modulator. Consequently, the background art disclosed in Patent document 7 operates accurately only when a DC offset and an I/Q phase mismatch are not present.
The background art disclosed in Patent documents 8, 9 is problematic in that the accuracy of an orthogonal demodulator which is used as a detecting system in an operation to compensate for an I/Q phase mismatch and an I/Q amplitude mismatch is responsible for an error of the compensating process. Specifically, a highly accurate compensating process requires an orthogonal demodulator having a high I/Q accuracy. However, a compensating process is performed because an orthogonal modulator having a high modulating accuracy is not practically available, and it is contradictory to require an orthogonal demodulator having a high I/Q accuracy as a means for such a compensating process. In an operation to compensate for an I/Q phase mismatch, if a DC offset remains in an orthogonal demodulator, then since the DC offset is reflected as an offset of a compensation quantity for correcting a transmission baseband signal, it leads to an increase a carriage leak of the orthogonal modulator. Though a means for compensating for the DC offset in the orthogonal demodulator may be provided and a compensating process may be performed on the orthogonal modulator after a compensating process is performed on the orthogonal demodulator, no means for compensating for the DC offset in the orthogonal demodulator is disclosed in Patent documents 8, 9.
As background art disclosed in Patent documents 8, 9 employs an orthogonal demodulator for a compensating process, after an output signal from the orthogonal demodulator is converted into a digital signal by an A/D converter, an I/Q mismatch quantity is determined, and a processing sequence is carried out to determine a compensation quantity for compensating for the I/Q mismatch. Inasmuch as it is necessary to determine an I/Q mismatch quantity and a compensation quantity from the data obtained within the range of the limited resolution of the ND converter, the accuracy of the compensation quantity is lowered. Patent documents 8, 9 fail to disclose a method of solving such a problem.
Patent document 1: JP-A No. 2002-252663;
Patent document 2: JR-A No. 08-213846;
Patent document 3: PC(WO) No. 09-504673;
Patent document 4: JP-A No. 2004-007083;
Patent document 5: PC(WO) No. 2004-509555;
Patent document 6: International publication No. 2003/101061 pamphlet;
Patent document 7: JP-A No. 06-350658;
Patent document 8: JP-A No. 2004-274288; and
Patent document 9: JP-A No. 2004-363757.